A Reconfigurable FFT Architecture for Variable Length and Multi-streaming WiMax Wireless OFDM Standards

This paper presents a reconfigurable FFT architecture for variable length and multistreaming WiMax wireless standard. The architecture processes 1 stream of 2048-pt FFT, up to 2 streams of 1024-pt FFT or up to 4 streams of 512-pt FFT. The architecture consists of 11 SDF pipelined stages and radix-2 butterfly is calculated in each stage. The sampling frequency of the system is varied in accordance with FFT length. The wordlength and buffer length in each stage is configurable depending on the FFT length. Latch-free clock gating technique is used to reduce power consumption. The architecture is synthesized for Virtex-6 XCVLX760 FPGA. Experimental results show that the architecture achieves the throughput as required by the WiMax standard and the design has additional features compared to the previous approaches. The design used 1% of the total available FPGA resources and maximum clock frequency of 313.67 MHz was achieved.